1. Field of the Invention
This invention relates generally to handling articles having intrinsic polar characteristics. More particularly, the invention relates to identifying the orientation of such characteristics within the articles and to sorting the articles into groups of the same orientation of the characteristics within the articles. The invention is of particular interest to the assembly of semiconductor chips, such as diodes. For instance, in the manufacture of varistors, it becomes necessary to group the diodes according to the orientation of their p-n junctions prior to the attachment of leads to the diodes.
The present invention is discussed with respect to sheet-diffused diode chips. However, it should be understood that any reference in the disclosure to this product is for illustrative purposes only, and that such reference is not intended to limit the scope of the invention.
2. Discussion of the Prior Art
Conventionally, semiconductor devices are formed in great numbers as individual units in a single wafer. The wafer is subjected to a series of processing steps. The number and the sequence of these steps vary, depending upon the complexity of the final product. Upon completion of the steps the wafer is divided into the individual units. These units are commonly referred to as dice or chips.
Depending on the previous manufacturing steps, the chips may be complex integrated circuits or they may be simple diodes. One method of manufacturing diodes is to generate within the body of the wafer a single rectifying p-n junction parallel to the two major surfaces of the wafer. The junction separates two doped semiconductor regions or domains, each of opposite conductivity type with respect to the other. Each domain lies adjacent to and in contact with one of the major surfaces. The domains are formed by well known methods. For instance, impurities of one conductivity type, such as phosphorous are diffused from one surface into the semiconductor wafer which is comprised of single-crystal silicon material, predoped with impurities of the opposite conductivity type, such as boron.
The wafer then becomes a single, large diode. When both major surfaces of the wafer are metallized, they become the two terminals of the diode. Subsequent to the metallization in one of various conventional ways the diode wafer is separated into a number of small diode chips. Each of these chips has diode characteristics since each chip includes its respective portion of the previously formed p-n junction between its two major surfaces. Diodes formed by the described process of uniformly diffusing impurities through the wafer to form a single large diode and then dividing the wafer into small diode chips are referred to as sheet-diffused diodes. A number of known methods are available to divide the wafer into the chips.
One of these methods for the wafer entails selectively masking one of its major surfaces with small steel discs. The surface is then subjected to a grit blast process which erodes material between the discs until the wafer is completely separated into a plurality of small islands, each one of which is covered by one of the small discs. These discs are usually of circular shape and the erosion process leaves each of the formed diode chips with slightly sloped edges resulting in the major surfaces of the chips being of different sizes.
Another known method of spearating the wafers into chips involves scribing the wafer with two sets of parallel lines. The lines of one set intersect the lines of the other. The wafer is then flexed to break it along the scribed lines. When it is desired to separate the wafer into rectangular chips the line spacing of one set of lines is increased with respect to the line of spacing of the other set.
Another method of separating the chips from the wafer is by sawing the wafer, mounted on a solid support, with what is referred to as a gang saw. A gang saw has a plurality of blades which are mounted in parallel. Two cutting operations by the gang saw, one at right angles to the other, separate each wafer into a plurality of square chips.
Handling the individual chips efficiently in further manufacturing operations becomes a concern because of the small size of the chips and their intrinsic polar characteristics. These further manufacturing operations include the attaching of leads to the metallized terminal areas on the two major surfaces of the chips and the encapsulation of the chips to protect them from environmental influences that could destroy or adversely affect their electrical characteristics. For some products, such as simple diodes, it is not necessary to know the orientation of the p-n junctions within the chips with respect to the leads prior to the encapsulation of the chips. Leads are simply attached to each of the terminal areas and the chips are then encapsulated to form completed devices. The devices are then tested and marked to indicate their polarities, namely, the orientation of the p-n junctions of the diodes within the devices.
In other manufacturing methods, the diode chips are mounted in a known orientation to a header or to a header stud. Then, the second stud or lead is attached to the other side of the chip to complete the diode. These studs or leads may indicate the polarity of the diode. Or the diode may be tested again after encapsulation and marked according to the outcome of the test to indicate orientation of its p-n junction within the finished device.
As can be seen from the last example, it may be desirable to know the orientation of the p-n junction within each of the diode chips before the diodes become encapsulated. Some ways are already available to recognize the orientation of junctions within the chips. For instance, when diodes are not sheet diffused, but instead junctions ae diffused as discrete regions. One of the terminals of each chip occupies only a portion on one of the major surfaces. This terminal is recognized by a small metal contact dot to which a lead has to be attached.
Also, the separation of sheet diffused diodes by grit blasting can be carried out to make the orientation of the p-n junctions in the chips identifiable. It simply becomes necessary to orient the direction of the p-n junctions of all wafers so that the surface facing toward the impinging grit lies consistently adjacent to the same conductivity type domain.
If, for instance, the surface associated with the positive conductivity type domain is facing up toward the impinging grit, the grit blasting operation cuts the positive conductivity type or p-type surface except where it is protected by the small steel discs. The opposite major surface, however, facing away from the impinging grit is cut only to the extent that it takes to cut through the thickness of the wafer. The separated diode chips take the shape of truncated cones the two major surfaces of which are spaced by sloped edges. The polarity or orientation of the p-n junction within each diode chip is known by the size of one major surface of the chip with respect to the other.
When, however, sheet-diffused diodes are separated from the wafer by either scribing and breaking or by sawing their edges are substantially perpendicular between the two major surfaces. When both major surfaces of the diodes are coated with the same type of contact metal, the polarity of the diodes, meaning the orientation of the p-n junctions within the diode chips, is not readily ascertainable. In some prior art processes in which the orientation of the diodes has to be known to permit the diodes to be correctly assembled, electrical testing is used to determine the orientation of the diodes.
For instance, in a process for making a varistor, two diodes are assembled in parallel between two leads. However, for the varistor to have its desired characteristics, the polarities of the diodes are reversed with respect to each other. The assembly of the diodes presupposes knowledge about the orientation of the diodes.
In the past, these diodes have been assembled by a multi-station and multi-function apparatus. The apparatus receives the diode chips from a conventional vibratory feeder bowl. The chips vibrate in a single file along a track to a test point. At that point a probe is lowered toward the track. The probe contacts the chip located at the test point and performs a test to its polarity of its p-n junction. Depending on the outcome of this test, the chip is transferred either to one or another track. Since this test is performed on all chips in sequence, they become sorted into two groups depending on the orientation of the p-n junction in each of the chips.
The two tracks feed a magazine of a multi-position assembly apparatus. The apparatus includes a multi-position turntable. At a first position of the turntable, a first lead is placed onto an assembly fixture. Several of the fixtures are located evenly spaced along the periphery of the turntable. The turntable indexes and advances the fixtures in sequence to a second position.
At the second position there a dual vacuum arm picks up two chips, one from each of the two tracks and places them next to each other over one end of the first lead. Then, a second lead is placed with one end over the top of the two positioned chips so that the two leads extend away from the chips and from each other. As the table indexes to advance each of the fixtures so loaded with leads and chips in sequence to a solder reflow station, the chips and the leads become soldered to each other to form the device.
The operation of such an assembly apparatus is, of course, complex. The apparatus executes many mechanical functions and requires many linkages. A malfunction in any of the linkages requires a total shutdown of the assembly operation. Consequently, The average hourly output of the apparatus is often decreased by downtimes. It is, therefore, desirable to simplify the operation of assembling sheet diffused diodes into varistors.